The present invention relates generally to semiconductors and more specifically to a manufacturing method for dual damascene semiconductors.
In the process of manufacturing integrated circuits, after the individual devices such as the transistors have been fabricated in the silicon substrate, they must be connected together to perform the desired circuit functions. This connection process is generally called xe2x80x9cmetallizationxe2x80x9d and is performed using a number of different photolithographic and deposition techniques.
One metallization process, which is called the xe2x80x9cdamascenexe2x80x9d technique, starts with the placement of a first channel dielectric layer, which is a silicon dioxide or other oxide layer, over the semiconductor devices. A first damascene step photoresist is then placed over the dielectric layer and is photolithographically processed to form the pattern of the first channels. An anisotropic etch, an oxide etch, is then used to etch out the channel dielectric layer to form the first channel openings. The damascene step photoresist is then stripped and a conductive material is deposited in the first channel openings.
Some conductive materials, such as copper, require preparatory steps before deposition. An optional adhesion material, such as tantalum or titanium, is deposited followed by a barrier material, such as tantalum nitride or titanium nitride. The combination of the adhesion and barrier material is collectively referred to as xe2x80x9cbarrier layerxe2x80x9d herein. The barrier layer is used to prevent failure causing diffusion of the conductive material of the channels into the dielectric layer and the semiconductor devices. A seed layer is then deposited on the barrier layer to form a conductive material base, or xe2x80x9cseedxe2x80x9d, for subsequent electro-deposition of the conductive material.
The conductive material is then deposited in the first channel openings and subjected to a chemical-mechanical polishing process which removes the materials above and outside the first channel dielectric layer. Chemical-mechanical polishing (referred to as xe2x80x9cCMPxe2x80x9d) typically involves mounting a wafer face down on a holder and rotating the wafer face under pressure against a polishing pad mounted on a polishing platen, which in turn is rotating or is in orbital state. A slurry or slurries containing a chemical that chemically interacts with the facing wafer layer and an abrasive that physically removes that layer is flowed between the wafer and the polishing pad or on the pad near the wafer. A combination of the chemical reaction between the slurry and the layer being polished and the mechanical interaction between abrasives within the slurry and the layer being polished cause the planarization of the layer. During IC fabrication, this technique is commonly applied to planarize various wafer layers, such as dielectric layers, metallization, etc.
With the CMP, the conductive material is formed into the first channel dielectric layer to form the first conductive channels in a xe2x80x9cdamascenexe2x80x9d process. After the CMP process the conductive material in the channels is passivated by deposition of a high dielectric constant dielectric layer. The dielectric layer protects the conductive material from oxidation and is intended to prevent the diffusion of the conductive material into subsequent dielectric layers.
For multiple layers of channels, the xe2x80x9cdual damascenexe2x80x9d technique is used in which the channels and vias are formed at the same time. In one example, the via formation step of the dual damascene technique starts with the deposition of a thin dielectric etch stop layer, such as a silicon nitride, over the first channels and the first channel dielectric layer. Subsequently, a via dielectric layer is deposited on the etch stop layer. This is followed by deposition of a thin via dielectric etch stop layer, generally another nitride layer. Then, a via step photoresist is used in a photolithographic process to designate round via areas over the first channels.
A stop layer etch, generally a nitride etch, is then used to etch out the round via areas in the via nitride. The via step photoresist is then removed, or stripped. A second channel dielectric layer is then deposited over the via dielectric stop layer and the exposed via dielectric layer. A second damascene step photoresist is placed over the second channel dielectric layer and is photolithographically processed to form the pattern of the second channels. An anisotropic etch is then used to etch the second channel dielectric layer and the via dielectric layer to form the second channel openings and the via areas down to the thin etch stop layer above the first channels. The damascene photoresist is then removed, and a stop layer etch process removes the via etch stop layer above the first channels in the via areas.
For conductive materials such as coppers as previously described, a barrier layer is then deposited to coat the via openings and the second channel openings. Next, a seed layer is deposited on the barrier layer. This is followed by a deposition of the conductive material in the second channel openings and the via openings to simultaneously fill the second channel and the vias. A second CMP process defines the second channel and leaves the two vertically separated channels connected by a cylindrical via. Again, after the CMP process, the conductive material in the channels is passivated by deposition of another dielectric layer. The dielectric layer protects the conductive material from oxidation and is intended to prevent the diffusion of the conductive material into dielectric layers.
The use of the damascene techniques eliminates metal etch and dielectric gap fill steps typically used in the metallization process. The elimination of metal etch steps is important as the semiconductor industry moves from aluminum to other metallization materials, such as copper, which are very difficult to etch.
Unfortunately, as the size of semiconductor devices is decreased in order to increase speed and reduce cost, electro-migration increases in the channels connecting the semiconductor devices. Electro-migration is the movement of conductive material along channels and vias due to current flow in the channels and vias. The causes of electro-migration are not fully understood for all the different types of semiconductor devices, but electro-migration can lead to voids in the channels and vias, which lead to reduced performance or failure of the semiconductor devices. Solutions for eliminating electro-migration have been long sought by, but have eluded, those skilled in the art.
The present invention provides a method for reducing electro-migration in conductive material channels in semiconductors due to poor adhesion and CMP-induced polycrystallization and dislocations by performing initial planarization using reduced mechanical polishing pressure below three pounds/square inch at the surface of the conductive material channels and introducing a larger particle size abrasive to provide a rough conductive material contact areas at the surface of the conductive material channels after initial planarization.
The present invention further provides a method for reducing electro-migration along conductive material channels in semiconductors due to poor adhesion between barrier and conductive layers by providing a CMP roughening step after a conventional CMP step.
The present invention further provides a method for reducing electro-migration in conductive material channels in semiconductors due to CMP-induced polycrystallization and dislocations by significantly reducing the mechanical polishing parameters for the chemical-mechanical polishing process.
The above and additional advantages of the present invention will become apparent to those skilled in the art from a reading of the following detailed description when taken in conjunction with the accompanying drawings.